Startup register values for 3Dfx/Voodoo 3 BIOS v2.15.12-SD

   Name       Default         Performance modified           Comments

 pciInit0   0x0584FB04            0x1E041840           // PCI bus I/O options
 miscInit0  0x00000000            ----"----
 miscInit1  0x00008001            0x08008001           // Misc options
// miscInit1  0x00008001            0x08000001
 dramInit0  0x0C1FA9E9            0x0C12A028           // Memory timings
 dramInit1  0x4056C601            0x405603FF           // Memory access options
// dramInit1  0x4056C601            0x406703FF
 agpInit0   0x0000049E            0x0000049F           // AGP options
 pllCtrl1   0x0000720D (166 MHz)  0x00008A0D (200 MHz) // Core/Memory clocking
 pllCtrl2   0x00000000            ----"----            // Has no effect now
 sgramMode  0x00000037            ----"----


Notes:

1) The memory timings are for SDRAM-type memory with 5.0 ns access time,
   operating at 200 MHz. If your memory access time is greater than 5.0 ns,
   the timings may be too aggressive (in fact, they are aggressive even for
   5.0 ns). This may result in visual glitches and/or lockups.
2) In SGRAM version, memory timings and configs will be different. Do not use
   the above values.
3) The values should work with Voodoo 4/5 SDRAM versions as well.
4) pllCtrl2 has no effect since BIOS v1.xx (before that, pllCtrl1 and pllCtrl2
   used to control core and memory timings separately).
5) A maximum safe size of the PCI fifo read buffer was found to be 32 (bits 25
   to 20 in pciInit0), which now it is set at. Above that, it was causing
   lockups. This is for i400BX chipset - other chipsets with other CMOS settings
   might have different max values, so you may need to lower that for
   compatibility. The default value was 24.
6) PCI fifo low watermark has been increased from 1 to 16 (half of the first
   in/first out buffer, which should implement Clark's algorithm for efficient
   buffering, i.e. not to start refilling the buffer until available room >=
   1/2 * total size). The value is located at bits 6 to 2 in pciInit0.
7) AGP request priority has been changed from normal to high. This seems to be
   capable of causing severe "bus congestion" on some systems, especially VIA
   based, manifesting itself in general sluggishness when video I/O is in
   progress (like chopping sound in games).